1. Field of the Invention
The present disclosure relates to an on-chip functional debugger and a method of providing on-chip functional debugging.
2. Discussion of the Related Art
Validation of new chip designs involves a process of debugging of faults observed during various phases of testing. The debugging activity targets the identification of the causes of the fault or bug. Once a cause of defect is isolated, it is easy to replicate the problem on CAD (Computer-aided design) simulation environment and to resolve it. However poor visibility of internal nodes results in significant debugging time for complex problems. Owing to this limitation, silicon debugging remains an unsystematic process involving multiple variables.
Existing design methodologies do offer some debugging techniques. Some of the techniques are listed below:
JTAG (Joint Test Action Group) Interface. This interface is very slow and is therefore useful only for signals in KHz frequency domain.
Scan Chains are capable of debugging of manufacturing faults only.
E-beam Methodology. This is a complex and costly method and requires special facilities which are not easily available.
A specialized interface like Chipscope available only for FPGAs (Field-programmable gate array). It does not offer real time probing, is hardware intensive and the depth of signals probing is dependent on size of internal memory bank